TXMC633

TXMC633 Reconfigurable FPGA with 64 TTL I/O or 32 Diff./M-LVDS I/O

XMC module providing a user configurable Xilinx XC6SLX45T or Xilinx XC6SLX100T FPGA. The TXMC633-x0R has 64 ESD-protected TTL lines, the TXMC633-x1R provides 32 differential I/O lines using EIA-422 / EIA-485 compatible, ESD-protected line transceivers. The TXMC633-x2R provides 32 TTL and 16 differential I/Os, the TXMC633-x3R has 32 M-LVDS I/O lines and the TXMC633-x4R provides 32 TTL I/O and 16 M-LVDS I/O lines. All lines are individually programmable as input, output or tri-state. The receivers are always enabled, which allows determining the state of each I/O line at any time. Each TTL I/O line has a pull-up resistor. The pull-up voltage is selectable to be either +3.3V or +5V. The differential RS-485 I/O lines are terminated by 120Ω resistors and the differential M-LVDS I/O lines are terminated by 100Ω resistors.

For custom specific I/O extension or inter-board commuication the TXMC633 provides 64 FPGA I/Os on P14 and 3 FPGA Multi-Gigabit transceiver on P16. P14 I/O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface.

The FPGA is configured by a platform flash SPI flash or via PCIe download. The flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”). User applications for the TXMC633 with XC6SLX45T-2 FPGA can be developed using the design software ISE Project Navigator and Embedded Development Kit (EDK).

The TXMC633 provides front panel I/O via a HD68 SCSI-3 type connector and rear panel I/O via P14 and P16.

A wide range of drivers is available: Linux, LynxOS, Integrity, QNX, VxWorks and Windows. All drivers - except the Windows drivers - are supplied as C source code.